SPI performance

Questions on control of serial busses
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YahooArchive
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Joined: Fri Oct 19, 2012 5:11 am

SPI performance

Post by YahooArchive » Thu Feb 14, 2013 1:02 am

Hello All,

I am trying to use a SPI 16-bit A/D and 16-bit D/A converter to do some things
with audio. For now I just wrote some code that reads A/D samples, and writes
those samples back out to the D/A. I am only getting about 12000 samples per
second of throughput, waaay too slow. My devices are capable of much higher
speeds.

This is the meat of my SPI routine for the A/D...

while j
if (IN(adcSDO)) then value = value or j
adcSCK = 1
adcSCK = 0
j = j >> 1
loop

and D/A...

while i
dacSDI = (i and dacA)
dacSCK = 1
dacSCK = 0
i = i >> 1
loop


Everything I have read says this should be fast. What am I doing wrong?



YahooArchive
Posts: 1463
Joined: Fri Oct 19, 2012 5:11 am

Re: SPI performance

Post by YahooArchive » Thu Feb 14, 2013 1:03 am

Sorry I forgot to mention my hardware is the Coridium SuperPro and I am
programming with their BASIC Compiler.

YahooArchive
Posts: 1463
Joined: Fri Oct 19, 2012 5:11 am

Re: SPI performance

Post by YahooArchive » Thu Feb 14, 2013 1:03 am

Are you using IO or OUT for the clocks?

OUT will be 3 times faster as IO also sets the direction.

Also if the pin number >32 then that slows the operation by about 30%

the timings I get for a SuperPRO in BASIC

IN(1) 210 nsec
IO(1) 930 nsec -- as input
OUT(1) 300 nsec
IO(1) 960 nsec -- as output
IN(35) 320 nsec

IN,IO and OUT are flexible and easy to use, but with everything there is a
tradeoff, and that tradeoff is speed. You can write directly to the registers,
and maybe improve on that with variables as pointers.

But to really get the max performance you'll want to engage the SPI or SSP
hardware, where you can run bit rates up beyond 10 MHz.

YahooArchive
Posts: 1463
Joined: Fri Oct 19, 2012 5:11 am

Re: SPI performance

Post by YahooArchive » Thu Feb 14, 2013 1:04 am

I was using IO(n) as shown below...

#define dacSDI IO(32) 'AKA P1.0, or "B0"
#define dacSCK IO(36) 'AKA P1.4, or "B4"
#define dacCS IO(41) 'AKA P1.9, or "B9"
#define adcCONV IO(33) 'AKA P1.1, or "B1"
#define adcSCK IO(40) 'AKA P1.8, or "B8"
#define adcSDI IO(42) 'AKA P1.10, or "B10"
#define adcSDO IO(46) 'AKA P1.14, or "B14"

So would that translate to...

#define dacSCK OUT(36) etc?

Also when you say pin > 32 is this based on the IO(n) number? Or actual IC Chip
pin number?

YahooArchive
Posts: 1463
Joined: Fri Oct 19, 2012 5:11 am

Re: SPI performance

Post by YahooArchive » Thu Feb 14, 2013 1:05 am

>
> So would that translate to...
>
> #define dacSCK OUT(36) etc?

yes

> Also when you say pin > 32 is this based on the IO(n) number? Or actual IC
Chip pin number?
>

It refers to the n in IO(n). The IO function is a runtime routine that compares
n to 32 and uses FIO0 for those less than 32, then checks for less than 64 and
uses FIO1, and so on. So as those tests are made, FIO0 occurs first so it is a
little faster.

YahooArchive
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Re: SPI performance

Post by YahooArchive » Thu Feb 14, 2013 1:05 am

Thank you! The throughput is now more than twice as fast. Good enough for most
things I want to do. Still not fast enough for some things however. I am very
interested in learning more about the LPC1756 internal SPI handler. I will start
a new thread about it.

YahooArchive
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Re: SPI performance

Post by YahooArchive » Thu Feb 14, 2013 1:06 am

Does anyone have any experience with using the SPI handler that is built in to
the LPC1756(SuperPro)? I am trying to use 3 or more SPI devices that each have
their own chip select, but share SCK, MISO, MOSI signals. I am confused about
the whole Master/Slave thing. In the case of writing a value to a D/A, I assume
the '1756 is the Master and it is a one way conversation with data being clocked
out the MOSI pin. BUT, if I want to get data from an SPI device such as an A/D,
do I now have to configure the '1756 to be a slave? Or can it receive data in
MISO, while still being the master? What needs to be done with the SSEL pin when
a master wants to receive data from a slave?

YahooArchive
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Re: SPI performance

Post by YahooArchive » Thu Feb 14, 2013 1:06 am

Generally the way SPI works is you have a master and one or more slaves. The
master provides the clocks. The master will select a device via the chip select
and sends/clocks out the command while the slave is sending back status or a
response to the command in sync with the master clock. So data is going both
ways simultaneously on the MOSI and MISO lines. It can then change chip select
lines and talk to another device on the same MOSI/MISO lines. The slave cannot
initiate a conversation.

Your A/D device should have info about what is being sent out as it is receiving
data from the master.

The SuperPro can be the master or a slave to another controller.

jw

YahooArchive
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Re: SPI performance

Post by YahooArchive » Thu Feb 14, 2013 1:12 am

Got this working now, thanks for your reply. This is definitely the way to go
for SPI stuff. It is so fast, I have to lower the clock speed to the peripherals
so as not to exceed their specifications.

-dg

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